STELLAR: Structure-guided LLM Assertion Retrieval and Generation for Formal Verification

In the ever-evolving field of formal verification (FV), SystemVerilog Assertions (SVAs) play a critical role in ensuring the accuracy and functionality of hardware designs. Traditionally, the creation of these SVAs has been a labor-intensive task, prone to human error and requiring significant manual input. To address these challenges, researchers have turned towards leveraging large language models (LLMs) which have the potential to either generate new assertions from the ground up or incorporate existing knowledge. However, one aspect that has been largely overlooked in these attempts is the importance of maintaining structural consistency and leveraging existing patterns from previous, expert-crafted assertions. Enter STELLAR, a groundbreaking framework unveiled in a recent paper submitted to arXiv. STELLAR represents an innovative leap in the automation of SVA generation by incorporating structural similarities, thereby enhancing both the efficiency and reliability of the assertions produced. By representing Register-Transfer Level (RTL) blocks as Abstract Syntax Trees (ASTs), STELLAR ensures that newly generated assertions are not only correct but also structurally aligned with existing standards. This approach is particularly significant as it offers a solution that bridges the gap between manual expertise and machine-generated precision. The implications of such advancements are vast, promising improvements in the overall quality of hardware verification and the optimization of workflows in technological design and production processes. This paper positions STELLAR at the forefront of technological innovations, setting a new standard for future developments in the field of formal verification.